The impacts of on-chip metal connective lines, power grids, heat sink along with packaging, and dummy fills on a 2 mm-long, 30 μm-wide on-chip dipole antenna pair characteristics were investigated with qualitative analysis. On-chip antenna pair transmission gain has been improved by 9 dB at 20 GHz by employing a 0.35 mm thick diamond layer between silicon substrate and heat sink. Extensive simulations were performed by three-dimensional software HFSS to explore the interfering effects of these metal structures and placements on the transmission gain, phase, impedance and radiation pattern for integrated dipole antenna pair. According to the results of experiment and simulations, several empirical linear formulas for antenna pair gain and phase in interfering circumstances were obtained using numerical fit. A set of design rules for on-chip antenna was summarized for wireless interconnection.